1. Technical Field
The present invention relates to a semiconductor memory cell and a semiconductor device, and more particularly, to a semiconductor memory cell and a semiconductor device having a buried bit line.
2. Related Art
As the degree of integration of semiconductor devices is increased, channel lengths of transistors are gradually reduced. However, the reduction of the channel lengths of the transistors causes short channel effects such as drain induced barrier lowering (DIBL), a hot carrier effect, and punch-through. To solve this problem, various methods such a method of reducing a depth of a junction region or a method of relatively increasing a channel length by forming a recess in a channel region of a transistor have been suggested.
However, as the integration density of the semiconductor memory devices, for example, dynamic random access memories (DRAMs) increases, fabrication of transistors having a smaller size is demanded. Accordingly, it is difficult to satisfy the desired device dimension with a current planar transistor structure in which a gate electrode is formed on a semiconductor substrate and junction regions are formed at both sides of the gate electrode even when scaling the channel length. To solve this problem, a vertical channel transistor structure has been suggested.
In recent years, there is a problem in that coupling capacitance between bit lines is increased since a buried bit line interferes with a bit line junction region due to reduction of a device size when the vertical channel transistor structure is formed. Thus, when a given buried bit line is activated, another buried bit line neighboring the given bit line may also be activated, causing a problem where data stored in a cell cannot be read properly due to noise generated when the data is amplified in a sense amplifier.